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sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? ultra high speed asynchronous operation ? fully static, no clocks ? multiple center power and ground pins for improved noise immunity ? easy memory expansion with ce\ and oe\ options ? all inputs and outputs are ttl-compatible ? single +3.3v power supply +/- 0.3% ? data retention functionality testing ? cost efficient plastic packaging ? extended testing over -55oc to +125oc for plastics options marking ? timing 12ns access -12 15ns access -15 20ns access -20 ? operating temperature ranges military (-55 o c to +125 o c) xt industrial (-40 o c to +85 o c) it ? package(s) ceramic flatpack f no. 307 plastic soj (400 mils wide) dj ceramic lcc ec no. 210 ? 2v data retention/low power l pin assignment (top view) 36-pin psoj (dj) 36-pin clcc (ec) general description the as5lc512k8 is a 3.3v high speed sram. it offers flexibility in high-speed memory applications, with chip enable (ce\) and output enable (oe\) capabilities. these features can place the outputs in high-z for additional flexibility in system design. writing to these devices is accomplished when write enable (we\) and ce\ inputs are both low. reading is accomplished when we\ remains high and ce\ and oe\ go low. as a option, the device can be supplied offering a reduced power standby mode, allowing system designers to meet low standby power requirements. this device operates from a single +3.3v power supply and all inputs and outputs are fully ttl-compatible. the as5lc512k8dj offers the convenience and reliability of the as5lc512k8 sram and has the cost advantage of a plastic encapsulation. 36-pin flat pack (f) available as military specifications ?mil-std-883 for ceramic ?extended temperature plastic (cots) 512k x 8 sram 3.3 volt high speed sram with center power pinout for more products and information please visit our web site at www.austinsemiconductor.com
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram truth table mode oe\ ce\ we\ i/o power standby x h x high-z standby read l l h q active not selected h l h high-z active write x l l d active s n o i t c n u f n i p 8 1 a - 0 as t u p n i s s e r d d a \ e we l b a n e e t i r w \ e ce l b a n e p i h c \ e oe l b a n e t u p t u o o / i 0 o / i - 7 s t u p t u o / s t u p n i a t a d v c c r e w o p v s s d n u o r g c nn o i t c e n n o c o n x = don?t care vcc gnd input buffer 4,194,304-bit memory array 1024 rows x 4096 columns i/o controls column decoder row decoder *power down ce\ oe\ we\ dq8 dq1 a0-a18 *on the low voltage data retention option.
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 absolute maximum ratings* voltage on vcc supply relative to vss vcc .........................................................................-.5v to 4.6v storage temperature .....................................-65 c to +150 c short circuit output current (per i/o)?........................20ma voltage on any pin relative to vss........................-.5v to 4.6v maximum junction temperature**..............................+150 c power dissipation ................................................................1w *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ** junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. electrical characteristics and recommended dc operating conditions (-55 o c < t a < +125 o c & -40 o c < t a < +85 o c ; vcc = 3.3v +0.3%) capacitance description sym -12 -15 -20 units notes i ccsp 80 70 60 ma "l" version only i cclp 60 50 40 ma i sbtsp 20 20 20 ma "l" version only i sbtlp 15 15 15 ma i sbcsp 15 15 15 ma "l" version only i sbclp 999ma max 3, 2 power supply current: standby conditions ce\ < v il ; vcc = max f = max = 1/t rc outputs open ce\ > v ih , all other inputs < v il , vcc = max, f = 0, outputs open ce\ > vcc -0.2v; vcc = max v in < vss +0.2v or v in > vcc -0.2v; f = 0 power supply current: operating

parameter conditions symbol max units notes input capacitance c i 9pf4 output capactiance co 6 pf 4 t a = 25 o c, f = 1mhz v in = 0
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 electrical characteristics and recommended ac operating conditions (-55 o c < t a < +125 o c or -40 o c to +85 o c; vcc = 3.3v +0.3%)

sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 input pulse levels ...................................................... vss to 3.0v input rise and fall times ......................................................... 3ns input timing reference levels ............................................... 1.5v output reference levels ........................................................ 1.5v output load ................................................. see figures 1 and 2 notes 1. all voltages referenced to v ss (gnd). 2. i cc limit shown is for absolute worst case switching of addr, addr\, addr, etc. 3. i cc is dependent on output loading and cycle rates. 4. this parameter is guaranteed but not tested. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. t lzce, t lzwe, t lzoe, t hzce, t hzoe and t hzwe are specified with cl = 5pf as in fig. 2. transition is measured 200mv from steady state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce, and t hzwe is less than t lzwe. 8. we\ is high for read cycle. 9. device is continuously selected. chip enables and output enables are held in their active state. 10. address valid prior to, or coincident with, latest occurring chip enable. 11. t rc = read cycle time. 12. chip enable and write enable can initiate and terminate a write cycle. 13. output enable (oe\) is inactive (high). 14. output enable (oe\) is active (low). 15. asi does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150c. care should be taken to limit power to acceptable levels. fig. 1 output load equivalent fig. 2 output load equivalent data retention electrical characteristics (l version only) ac test conditions description sym min max units notes vcc for retention data v dr 2v data retention current vcc = 2.0v i ccdr 6.5 ma chip deselect to data t cdr 0ns4 operation recovery time t r 20 ms 4, 11 conditions ce\ > v cc -0.2v v in > v cc -0.2 or 0.2v 3.3v q 353 ? 5 pf 319 ? q 30 pf r l = 50 ? v l = 1.5v z o =50 ?
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 low v cc data retention waveform read cycle no. 1 1, 2 (address controlled, ce\ = oe\ = v il , we\ = v ih ) read cycle no. 2 (we\ = v ih ) 1234 1 23 4 1 23 4 1 23 4 1234 don?t care undefined 123456 1 2345 6 1 2345 6 1 2345 6 123456 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 12345 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 12345 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 1234 1 23 4 1 23 4 1 23 4 1 23 4 1 23 4 1 23 4 1234 123456 1 2345 6 1 2345 6 1 2345 6 1 2345 6 1 2345 6 1 2345 6 123456 data retention mode 4.5v 4.5v v dr > 2v v dr t cdr t r v cc ce\ v ih - v il - address t rc 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 12345678901 1 234567890 1 1 234567890 1 1 234567890 1 1 234567890 1 12345678901 12 12 12 12 12 12 12 12 12 12 12 t oh t aa previous data valid data valid i/o, data in & out valid address t rc t aoe ce\ t lzoe t ace 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 12345 1 234 5 1 234 5 1 234 5 1 234 5 12345 1 1 1 1 1 1 1 1 1 1 1 1 data valid high-z t hzoe t hzce t pd i/o, data in & out icc t lzce t pu notes: 1. we\ is high for read cycle. 2. device is continuously selected. chip enables and output enables are held in their active state.
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 write cycle no. 1 1 (ce controlled) write cycle no. 2 1, 2 (write enabled controlled) 1234567890 1234567890 1234567890 1234567890 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 12345678901234567890123456 1 234567890123456789012345 6 1 234567890123456789012345 6 12345678901234567890123456 123456 123456 123456 123456 123456789012345678 1 2345678901234567 8 1 2345678901234567 8 123456789012345678 123456789012345678 1 2345678901234567 8 1 2345678901234567 8 123456789012345678 address t wc t cw ce\ t aw data valid t ah t as i/o, data out t wp1 t ds t dh we\ i/o, data in high-z high-z address t wc t cw ce\ 1234567890 1234567890 1234567890 1234567890 1234567890 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 1234567 1234567 1234567 1234567 1234567 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234567 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 12345678901234567 t aw data valid t ah t as i/o, data out 123456 123456 123456 123456 123456 1 notes: 1. chip enable and write enable can initiate and terminate a write cycle. 2. output enable (oe\) is inactive (high).
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 write cycle no. 3 1, 2, 3 (we controlled) address t wc t cw ce\ 123456789 123456789 123456789 123456789 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 1234567890123456789012 1 23456789012345678901 2 1 23456789012345678901 2 1234567890123456789012 1234567 1234567 1234567 1234567 1234567890123456 1 23456789012345 6 1 23456789012345 6 1234567890123456 12345678901234567 1 234567890123456 7 1 234567890123456 7 12345678901234567 t aw data valid t ah t as data out 123456 123456 123456 123456 2 notes: 1. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe . 2. chip enable and write enable can initiate and terminate a write cycle. 3. output enable (oe\) is active (low).
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 mechanical definitions* asi case #307 (package designator f) bottom view 36 1 c e2 a q *all measurements are in inches. d e b top view d1 s e l 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 pin 1 identifier area min max a 0.096 0.125 b 0.015 0.022 c 0.003 0.009 d 0.910 0.930 d1 0.840 0.860 e 0.505 0.515 e2 0.385 0.397 e l 0.250 0.370 q 0.020 0.045 symbol asi specifications 0.050 bsc
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 *all measurements are in inches. mechanical definitions* package designator dj min max a 0.128 0.148 a1 0.025 --- a2 0.082 --- b 0.015 0.020 b 0.026 0.032 c 0.007 0.013 d 0.920 0.930 e 0.435 0.445 e1 0.395 0.405 e2 e symbol asi specifications 0.050 bsc 0.370 bsc
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 mechanical definitions* asi case #210 (package designator ec) d e 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 pin 1 identifier area l2 l e b r d1 1 36 *all measurements are in inches. a a1 p min max a 0.080 0.100 a1 0.054 0.066 b 0.022 0.028 d 0.910 0.930 d1 0.840 0.860 e 0.445 0.460 e l l2 0.115 0.135 p --- 0.006 r 0.009 typ asi specifications symbol 0.050 bsc 0.100 typ
sram sram sram sram sram as5lc512k8 austin semiconductor, inc. as5lc512k8 rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing 1 -55 o c to +125 o c **options definitions l = 2v data retention / low power notes: 1. 883c process available with ceramic packaging only. device number package type speed ns options** process as5lc512k8 f -12 l /* as5lc512k8 f -15 l /* as5lc512k8 f -20 l /* device number package type speed ns options** process as5lc512k8 dj -12 l /* as5lc512k8 dj -15 l /* as5lc512k8 dj -20 l /* device number package t yp e speed ns options** process as5lc512k8 ec -12 l /* as5lc512k8 ec -15 l /* as5lc512k8 ec -20 l /* example: as5lc512k8f-12l/xt example: as5lc512k8dj-20l/883c example: as5lc512k8ec-15l/it

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